In a semiconductor memory such as SRAM, there is a proposed method of setting the timing of activating a sense amplifier in accordance with data being read into a dummy bit line from a dummy memory (see, for example, patent document 1). By connecting plural dummy memory cells to dummy bit lines, the timing of activating the sense amplifier is accelerated, and the inconsistencies in transistor characteristics are averaged out (see, for example, patent document 2). By changing the number of dummy memory cells connected to the dummy bit lines, the timing of activating a sense amplifier is adjusted (see, for example, patent document 3).    Patent Document 1: Japanese Laid-Open Patent Publication No. 2004-22070    Patent Document 2: Japanese Laid-Open Patent Publication No. 2003-323792    Patent Document 3: Japanese Laid-Open Patent Publication No. 2004-220721
The timing of activating a sense amplifier becomes faster as the number of dummy memory cells connected to dummy bit lines increases. Therefore, to optimize the timing of activating a sense amplifier, it is not possible to significantly increase the number of dummy memory cells. That is to say, in the conventional technology, it is not possible to significantly increase the number of dummy memory cells, and therefore the effect of averaging out the inconsistencies in transistor characteristics is limited.